The present invention relates to a jig for semiconductor wafers which is to be used in a heat treatment process in the semiconductor manufacturing and a method for producing the same, particularly to a vertical wafer board and a method for producing the same.
Conventionally, a heat treatment furnace was used for the diffusion or oxidation step of the semiconductor manufacturing, where the semiconductor wafers are subjected to a high temperature heat treatment. In this case, the semiconductor wafers placed on a wafer board which are accommodated in the furnace core tube formed of high purity silica glass such that a gas for heat treatment is introduced into the furnace core tube (process tube) for subjecting the wafer to the predetermined heat treatment.
On the other hand, there are now larger diameter wafers with the recent large scale integration of semiconductor to encourage the use of a vertical wafer board. However, when the extremities of a wafer are held in the grooves formed in the poles of the wafer board, deflections can be caused in itself due to the weight of its own and the temperature differentials throughout its plane with the result that a lack of crystal structure called "slip line" is produced in the wafer.
It is, therefore, proposed that the wafer board is provided with a wafer loading face in the form of a plane to support the wafer by means of an extensive plane of the loading face such that the formation of said "slip line" is prevented.
While vitreous glass was conventionally used as a material for such wafer board, a reaction sintered silicon carbide (SiC) material is used nowadays because high purity wafer products which are highly resistant to heat are accomplished by coating a substrate with a silicon carbide (SiC) film by chemical vapor deposition (hereinafter referred to as CVD-SiC).
However, there are still technical problems left unsolved with the vertical type reaction sintered silicon carbide (SiC) wafer board (hereinafter referred to as CVD board) which is coated with the CVD-SiC film as follows.
First, said CVD-SiC film is formed through a gas phase reaction. In this case, it is impossible to assure one hundred percent prevention of the extraordinary growth of silicon carbide (SiC) particles in the gas phase and some particles accumulate on the wafer loading face of the CVD board to form extraordinary protuberances in the loading face.
Second, suspended dust or particles in the CVD reaction tube tend to adhere to the wafer loading faces of the CVI) board before or during the CVD reaction. The silicon carbide (SiC) film is preferentially formed on such adhering dust or particles to come out in the form extraordinary protuberances in said loading faces.
Third, if utmost care is taken to prevent such formation of extraordinary protuberances by selecting CVD conditions, coarse crystallization in the CVD-SiC film results, again forming remarkable protuberances in the face.
It is known that extraordinary formation of protuberances or irregularities on the wafer loading faces causes a defect called "slip line" to occur in the backside of the wafer. The occurrence of such slip lines is remarkable in the case of a high temperature treatment step for oxidization and diffusion, thus making a major factor for lowering the heat treatment wafer yield.
According to the measurements obtained by the inventors in experiments, it is confirmed that the occurrence of the slip lines in the wafer becomes extremely conspicuous under a condition in case where the maximum surface roughness Rmax. exceeds 10 .mu.m in n times of the surface roughness measurements in the range of L.times.n.gtoreq.100 mm, where Lmm stands for the length to be measured and n stands for the number of the times of measurements.
This is considered due to an excessive concentration of load on the support portion in the backside of the wafer because the wafer is substantially point supported by the loading face instead of being supported by means of an extensive plane thereof.
Therefore, the inventors so far discussed methods of smoothing the wafer loading face coated with the CVD film through diamond grinding stone machining as a means for lowering the Rmax. of the wafer loading faces. However, machining by use of such a tool as a grinding stone creates a technical problem that pollution by impurities from machining by the grinding tool leads to the production of defective wafers in the oxidization and diffusion in the high temperature heat treatment process.
Further, particles of 1 .mu.m or less produced during the machining will adhere to the wafer loading face to provide a particle source in the step, further creating a technical problem as lowering the wafer production yield in the heat treatment as a result of particle adhesion onto the wafer.